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Chapter 1: XM104
8 . PCA9543 IIC Switch
The board’s serial IIC bus is wired to an EEPROM and a two-channel NXP (formerly
Philips Semiconductor) PCA9543 IIC bus switch on the XM104 (as shown in Figure 1-2,
page 10 ). The IIC bus switch provides bidirectional bus isolation and isolates the fixed
address Si570 and Si5368 devices from the main IIC bus of the board. The upstream side of
the switch connects to the FMC HPC connector. Only one of the two downstream ports is
utilized and it uses 3.3V signal levels. The downstream switch port interfaces to the two
Silicon Laboratories clock integrated circuits.
The PCA9543 is a bidirectional translating switch, controlled by the upstream board side
IIC bus. The PCA9543 must be initialized prior to attempting to communicate with the two
clock circuits, Si570 and Si5368, on the downstream IIC bus. The PCA9543 component data
sheet contains detailed application information and is available online at www.nxp.com .
The IIC address of this component is controlled by a combination of the board interface
and chip enable connections to the component inputs on the XM104. Signals GA0 and GA1
from the board are connected to the two address inputs A1 and A0 of the PCA9543
component. Xilinx boards provide GA0 and GA1 signal strapping to 3.3V and GND
signals creating different A0 and A1 address decodes on the PCA9543.
The IIC memory addressing protocol requires a bus master to initiate communication to a
peripheral device using a start condition followed by a device select code. The device select
code consists of a 4 bit Device Type Identifier and a 3-bit Address (A2, A1 and A0). A2 is
internally grounded inside the PCA9543. Bit 0 is used to indicate read/write. The Device
Type Identifier for the PCA9543 is 1110 binary. Table 1-9 defines the generic PCA9543
Device Select Code as well as specific Device Code Select address when the XM104 is
connected to a Xilinx board as defined in Table 1-1, page 7 .
Table 1-9:
PCA9543 IIC Switch Device Select Code
Bit 7:4 Device
Type Identifier
1110
Bit 3
0
Bit 2
GA0
Bit 1
GA1
Bit 0
LSB
Read/Write
Description
Connected to mezzanine FMC
HPC interface
The PCA9543 has a Control register which must be initialized by the IIC bus master to
enable the channel 0 downstream IIC port. Channel 0 must be enabled prior to attempting
to communicate with the two downstream programmable clock devices on the XM104.
After the IIC bus master enables PCA9543 channel 0 downstream IIC bus, the bus master
can communicate directly with the Si570 component or the Si5368 component without
further interaction with the Control register. The Control Register can be read by the IIC
bus master. Table 11 defines the PCA9543 Control Register.
Table 1-10:
PCA9543 Control Register
Bit 7:4
XXXX
Bit 3:2
XX
Bit 1
Channel 1
Enable (1)
Bit 0
Channel 0
Enable (2)
Notes:
1. Channel 1 is not connected on the XM104.
2. Channel 0 must be set to a logic 1 state by the IIC bus master prior to attempting
to communicate with the Si570 or the Si5368 components on the downstream IIC
bus.
16
www.xilinx.com
FMC XM104 Connectivity Card User Guide
UG536 (v1.1) September 24, 2010
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